In recent years, there has been a rapid progress in the development of semiconductor packages having an increased number of pins and a higher packaging density. In conventional semiconductor packages of this kind, lead-frame-type quad flat packages (QFPs) or the like have been in the mainstream but BGA packages using a substrate such as to have an advantage in terms of terminal density are now becoming mainstream.
In general, a BGA package manufacturing method in which a plurality of semiconductor devices are formed on one wiring substrate and are thereafter divided as individual semiconductor packages is in the mainstream. In recent years, multiarray-type wiring substrates on which a plurality of semiconductor devices are formed in two rows for the purpose of improving the productivity have been increased.
A BGA package technique of forming a plurality of semiconductor devices in two rows on a wiring substrate will be described. FIG. 21A shows an encapsulated state of semiconductor devices on a conventional wiring substrate, and FIG. 21B shows a state in which each semiconductor devices is divided as an individual package. In FIGS. 21A and 21B, chips and wires in encapsulated portions are expressed in a see-through fashion.
In FIGS. 21A and 21B, reference numeral 1 denotes a frame (connecting portion), reference numeral 2 a segment in the front row (a region divided in correspondence with each package), reference numeral 3 a front-row tie bar, reference numeral 4 a runner to the front row, reference numeral 5 a segment in the rear row (a region divided in correspondence with each package), reference numeral 6 a rear-row tie bar, reference numeral 7 a runner to the rear row, reference numeral 8 an opening, reference numeral 9 a positioning pin hole, reference numeral 10 a divided BGA package, reference numeral 11 a chip (semiconductor device), reference numeral 12 a wire, reference numeral 13 a resin encapsulated portion, reference numeral 14 a gate, and reference numeral 15 a runner before divergence.
As shown in FIG. 21A, the semiconductor devices have the chips 11 mounted on the segments 2 and 5 in a state where the segments 2 and 5 are connected to the frame 1 of the wiring substrate S. Each chip 11 is connected to substrate electrodes by wires 12. The chip 11 and the wires 12 are encapsulated in a resin to form the resin encapsulated portion 13.
The resin encapsulated portion 13 is formed so as to be a notch smaller than the size of the segment. This is for the purpose of preventing the resin from leaking out from the segments 2 and 5 of the wiring substrate S. The sides of the resin encapsulated portions 13 are formed parallel to the sides of the segments 2 and 5 of the wiring substrate S.
The segments 2 and 5 and the resin encapsulated portions 13 are orderly formed in matrix form. The runners 4, 7, and 15 are arranged on the frame 1. The runners 4, 7, and 15 form resin supply paths to the portion 13 to be resin encapsulated in an encapsulation mold. In the following description, “runners 4, 7, and 15” and the resin encapsulated portions 13 refer to cavities in the resin encapsulation mold or the resin material set in the cavities.
The openings 8 provided around the periphery of each of the segments 2 and 5 surround the segment except for corner portions of the segments 2 and 5. The portion 13 to be resin encapsulated has a gate 14 at one corner.
When resin encapsulation is performed by using the encapsulation mold, the encapsulation resin enters a region inside the wiring substrate S from the outside of the substrate and advances through the runners 15 in a direction perpendicular to a substrate peripheral edge of the frame 1. The runners 15 bend through an angle of 45 degrees at the corners of the segments 2 and 5 as the runners 4 to the front row and the runners 7 to the rear row.
The encapsulation resin enters the gates 14 of the portions 13 to be resin encapsulated through the runners 4 to the front row and the runners 7 to the rear row. The portions 13 to be resin encapsulated on the segments 2 and 5 in the front and rear rows are simultaneously supplied with the encapsulation resin from the runners 4 and 7.
At the time of gate break, i.e., when the runners 4, 7, and 15 are separated from the resin encapsulated portions 13 after setting of the resin in the above-described arrangement, a moment about an axis perpendicular to the axes of the runners 15 or a moment about an axis parallel to the axes of the runners 15 acts of the runners 4, 7, and 15, thereby bending the runners 4 and 7 at the gates 14.
In the conventional BGA package and the wiring substrate for the package, however, there is a difference of 45 degrees between the angle at which the runners 4 and 7 extend into the segments 2 and 5 and the angle at which the runners 15 extend into the frame 1 of the wiring substrate S.
Further, the runner distance by which the runners 15 and 7 extend to the segments 5 in the rear row is increased and the runners 15 and 7 are in close contact with the wiring substrate S through the entire length thereof. Therefore, the force necessary for separating the runners 15 and 7 from the wiring substrate S at the time of gate break is large.
Therefore, large stress acts in the runners 4, 7, and 15 at the time of gate break and obliquely works on the joint surfaces between the runners 4 and 7 and the resin encapsulated portions 13, and there is a problem that the possibility of portions of the runners 4 and 7 remaining at the gates 14, the possibility of the resin encapsulated portions 13 being chipped and the possibility of separation of the resin encapsulated portions 13 are increased thereby.
A method of using an arrangement in which the runners 15 extending from the outside of the wiring substrate S into the frame 1 are extended straight to central portions of the segments 2 and 5 without bending at any halfway points.
However, this method has a problem that the encapsulation resin tends to flow mainly at a central position on each portion 13 to be resin encapsulated without sufficiently spreading out in the cavity of the encapsulation mold for forming the resin encapsulated portions 13 while flowing. If the size of the portions 13 to be resin encapsulated is large, the possibility of voids (resin unfilled portions) remaining at the two corners closer to each gate 14 is increased.
Limiting this phenomenon requires ensuring a condition for enabling the encapsulation resin to flow while sufficiently spreading out in the cavity of the encapsulation mold, i.e., in the portions 13 to be resin encapsulated. Ensuring this condition requires increasing the width of each runner flow path immediately before reaching the portion 13 to be resin encapsulated so that the gate 14 is formed broader. However, this method is impractical for the reason described below.
In ordinary cases, plating portions are formed in predetermined regions on a wiring substrate corresponding to runners in order to ensure smooth runner separation at the time of gate break. Therefore, expansion of the plating portions is required for forming the gate 14 broader. Disadvantageously, expansion of the plating portions results in a reduction in wiring area on the wiring substrate.
A technique for lead-frame packages such as one technique disclosed in Japanese Patent Laid-Open No. 60-137049 is known. In the art disclosed in this publication, a method is proposed in which the die boning angle is inclined through 45 degrees to reduce the resistance of wires and a chip to the flow of an encapsulation resin or reduce stress after setting of the resin. Also, a method of inclining segments through 45 degrees from the orientation of runners to enable an encapsulation resin to flow smoothly is proposed in the art disclosed in Japanese Patent Laid-Open No. 62-152130.
These proposed methods can be said to be more effective than the conventional ones if the encapsulation resin flow is considered.
However, these methods are not an optimum solution to the above-described problem relating to gate break, the problem that voids (resin unfilled portions) occur at corners of a resin encapsulated portion, and other problems. Another related technique disclosed in Japanese Patent Laid-Open No. 4-276414 is known in which runners extending from the outside into a wiring substrate are without bending them on the way linearly led to centers of module sections (cavities) forming resin encapsulated portions. Cuts are formed in the wiring substrate extending from an outer peripheral edge of the same to the module sections.
In this arrangement, the runners are formed at positions corresponding to the cuts at the time of resin encapsulation. Portions of these runners placed adjacent to the module sections in correspondence with gates are not joined to the wiring substrate. This structure prevents portions of the runners from remaining at the gates at the time of gate break or prevents chipping of the resin encapsulated portions or separation of the resin encapsulated portions from the wiring substrate.
In this structure, however, the runners are supported in a cantilever manner at the gate since they are not joined to the wiring substrate through the entire runner distance to the gates. If the runner distance is increased, a load on the long runner acts on the narrow cross section of the gate, and a weak supporting structure results.
Therefore, there is a problem that when a force is applied in an unexpected direction to the runners by an erroneous operation or the like during transport of a plurality of semiconductor devices having resin encapsulated portions formed on the wiring substrate from the resin encapsulation step to the next gate break step for example, there is a possibility of the runners being broken in an unintended condition.